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- Path: nickel.as.arizona.edu!rwatkins
- From: rwatkins@nickel.as.arizona.edu (Ron Watkins)
- Newsgroups: comp.lang.c++
- Subject: Class for Digital Logic Gate?
- Date: 16 Apr 1996 22:36:07 GMT
- Organization: University of Arizona, Tucson, AZ
- Distribution: world
- Message-ID: <4l17cn$d2o@news.ccit.arizona.edu>
- NNTP-Posting-Host: nickel.as.arizona.edu
- Keywords: logic class
-
- I was wondering if anyone has implemented a class to support digital logic
- gates.
-
- I thought some about this, and it seems that a circuit can be specified as
- a graph where each gate is a node with a state. Each gate also has pointers
- to the nodes (other gates) where it's input comes from. Each gate also keeps
- track of how many outputs it has (fanout) when it allows a link from the next
- gate in the sequence to point to it's state.
-
- Propogation of logic could then be done using a breadth-first traversal of
- the graph (circuit). Child nodes would only need to be pushed onto the queue
- if a state change occured in the parent node.
-
- Has anyone done this before? Is there an existing model?
- --
- _ NICMOS project, Steward Observatory
- |_) _ ._ \ / _._|_ | o._ _ University of Arizona, Tucson AZ 85721
- | \(_)| | \/\/ (_| |_ |<|| |_> Phone: (520) 626-5122
- E-mail: rwatkins@as.arizona.edu
-